(1) Field of the Invention
The present invention relates to a semiconductor device comprising a refined transistor, and more particularly relates to countermeasures against an optical proximity effect in a fabrication process for semiconductor devices.
(2) Description of Related Art
Principal factors for causing variation in propagation delay time in design of a semiconductor integrated circuit (LSI) are an operation power voltage, a temperature, process variation and the like. Also, in LSI design, the operation of an LSI should be guaranteed even when all the conditions are the worst. A gate length of a transistor is a significant element for defining the operation of the transistor, and influence of variations in the gate length occupies a very large proportion in the process variation. Furthermore, in accordance with development in refinement of transistors, the gate length is reduced and hence their variation is increased. Therefore, since variation in the propagation delay time is increased and hence a design margin is increased, it has become difficult to provide LSIs with high performance.
In general, in the semiconductor fabrication process, photolithography process including resist application, exposure and development, etching process for patterning an element by using a resist mask and resist removing process are repeatedly carried out, so as to form an integrated circuit on a semiconductor substrate. Also in forming a gate of a transistor, the photolithography process, the etching process and the resist removing process are performed. In the exposure of the photolithography process, when the dimension of a pattern is smaller than the wavelength of exposing light, the error between a layout dimension set in the design and an actual pattern dimension formed on a semiconductor substrate is increased due to an optical proximity effect caused by influence of diffracted light.
Examples of the technique for overcoming this problem are super-resolution technique using a phase shift mask and OPC (optical proximity correction) technique for correcting the influence of the optical proximity effect by correcting a circuit pattern drawn on a mask.
FIG. 10 is a plan view showing a part of a semiconductor integrated circuit. FIGS. 11A and 11B are graphs for explaining an example of an OPC technique. FIG. 10 shows the layout of an N-channel type transistor typically used in a standard cell.
FIG. 10 shows a gate electrode 52, dummy gate electrodes 51 and 53 between which the gate electrode 52 is formed, and N-type impurity diffusion regions 7A1 located to both sides of the gate electrode 52. Lg denotes a gate length, Wg denotes a gate width, DWG denotes an adjacent gate length (the length of each dummy gate electrode), and S denotes a gate space (the distance between the gate electrode and each dummy gate electrode). Although an LSI has various dimensions, such as different gate lengths Lg, gate spaces S and adjacent gate lengths DGW, the differences between mask dimensions and dimensions on a finished product are corrected by the OPC technique. FIGS. 11A and 11B show how the finished gate length Lg varies according to variations in the adjacent gate length DGW when each gate space S is fixed. As shown in FIGS. 11A and 11B, before the OPC, with the variation in the adjacent gate lengths DGW from 0.1 μm to 0.5 μm, the finished gate length Lg changes from 0.11 μm to 0.16 μm when an original gate length on a mask is 0.10 μm. On the other hand, after the OPC, the finished gate length Lg changes only from 0.102 μm to 0.11 μm. This shows that the OPC technique can significantly improve the dependence of the finished gate length Lg on a pattern due to the influence of the optical proximity effect.
Furthermore, a method in which connection information between circuit elements including finished dimensions are fed back to a net list while an integrated circuit is subjected to OPC is also effective. This method is typified by Japanese Unexamined Patent Publication No. 2004-30382.
FIG. 12 is a flow chart showing a typical known fabrication method for a semiconductor integrated circuit using OPC. It is an object of the known art shown in FIG. 12 to determine the error between element values due to a rounded reflex angle resulting from exposure in the fabrication of a semiconductor device. A detector 51 detects an element pattern having a reflex angle from physical data indicating element patterns formed on a semiconductor substrate. An error calculator 52 calculates an error caused by rounding a part of the element pattern having a reflex angle during exposure. An element value calculator 53 calculates the variation in the value of the corresponding element based on the error calculated by the error calculator 52.